1. Field of the Invention
This invention relates to a semiconductor memory, and more particularly to a dynamic memory using a shared sense amplifier.
2. Description of the Related Art
In the ordinary dynamic memory, as shown in FIG. 6, one sense amplifier SA is used for each pair of digit lines. That is, each sense amplifier SA is provided for each digit line pair. Each digit line pair includes complementary bit lines (BL and BL). Data read out from a memory cell which is connected to one of bit lines BL and BL is supplied to the bit line and a potential difference between the paired bit lines is amplified by the sense amplifier.
With an increase in the integration density of the dynamic memory, memory capacitance Cs becomes smaller but bit line capacitance Cb is not reduced. As a result, the ratio Cb/Cs of bit line capacitance Cb to memory capacitance Cs becomes larger. That is, the potential difference between the paired bit lines obtained at the time of reading out memory cell data will become smaller, making it necessary to strictly set the sensitivity margin of the sense amplifier.
In order to solve the above problem, it is necessary to reduce the ratio of Cb/Cs. For this purpose, it is considered that (1) the length of the bit line is reduced to make bit line capacitance Cb small or (2) the area of the memory cell is increased to increase memory cell capacitance Cs. However, the former method has a problem that it is necessary to use a larger number of sense amplifiers because of the short length of the bit lines, and the latter method has a problem that the entire area of the memory chip is increased, making it difficult to enhance the integration density of the memory.
In order to solve the above problems, there has been proposed a so-called shared sense amplifier system in which a plurality of bit line pairs share the same sense amplifier. Such a shared sense amplifier system is disclosed in "ISSCC '79 technical digest", pp. 146-147, 1979 by Ilbok et al and Japanese Patent Publication No. 62-55234. For example, as shown in FIG. 7, two bit line pairs (BL.sub.1, BL.sub.1) and (BL.sub.2, BL.sub.2) share sense amplifier SA and one of the bit line pairs is selected by bit line selection clock signals (.phi.1, .phi.2) and selectively connected to the sense amplifier.
In the shared sense amplifier system, the sense amplifier is commonly used for a plurality of bit line pairs so that the number of sense amplifiers and the total length of the bit lines can be suppressed to a minimum. As a result, bit line capacitance Cb can be reduced and Cb/Cs can be set to be smaller, thereby making it possible to reduce the power consumption and attain a high speed access operation.
In order to meet the requirement of attaining the high speed access operation and low power consumption, a Vcc/2 precharge system in which the paired bit lines are precharged to a voltage level equal to half the Vcc power source voltage is mainly used. In this case, in order to sense the potential of approx. Vcc/2 at a high sensitivity and latch data of the bit line at high speed, a sense amplifier of CMOS construction (formed of a P-channel sense amplifier constituted by a P-channel transistor and an N-channel sense amplifier constituted by an N-channel transistor) is often used.
However, in order to transfer the signal at the high level Vcc, amplified by the sense amplifier, to the bit line, it is necessary to raise the voltages of the clock signals .phi.1 and .phi.2 supplied to the switching transistors Tn.sub.1 and Tn.sub.2 to a level higher than Vcc+V.sub.T, and the control circuit is inevitably complex.
As is disclosed by Fujii et al. in IE.sup.3 J. Solid-State Circuits, Vol. SC-21, No. 5, October 1986, a CMOS sense amplifier is known which has the structure illustrated in FIG. 7B and in which a transfer gate (or a resistor), which is always on, is connected between the N-channel SA and the P-channel SA, so that the CMOS sense amplifier has a sufficiently high sensitivity. This transfer gate can be used also as a switching transistor, in which case the adjacent memory-cell arrays share the N-channel SA only as is illustrated in FIG. 8. In this case, it is necessary to use two P-channel sense amplifiers SP.sub.1 and SP.sub.2 in correspondence with two bit line pairs (BL.sub.1, BL.sub.1) and (BL.sub.2, BL.sub.2) and commonly use a single N-channel sense amplifier SN. With this arrangement, the area performance cannot be significantly improved and the chip area cannot be reduced in comparison with the case where the shared sense amplifier system is not used and two P-channel sense amplifiers and two N-channel sense amplifiers are used for two bit line pairs.